summaryrefslogtreecommitdiffstats
path: root/drivers/char/agp/intel-agp.c
diff options
context:
space:
mode:
authorZhenyu Wang <zhenyuw@linux.intel.com>2010-08-27 11:08:57 +0800
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-07 11:16:43 +0100
commitf8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 (patch)
tree9211554f0542ce636aa1f14ffe58cfa832efa04d /drivers/char/agp/intel-agp.c
parent93f5f7f1249e76a5e8afbdab53f90b10c41fdb61 (diff)
agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char/agp/intel-agp.c')
-rw-r--r--drivers/char/agp/intel-agp.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 710af89b176..74461d177ba 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -12,6 +12,7 @@
#include <asm/smp.h>
#include "agp.h"
#include "intel-agp.h"
+#include <linux/intel-gtt.h>
#include "intel-gtt.c"