diff options
| author | Gerhard Sittig <gsi@denx.de> | 2013-07-22 14:14:40 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-27 17:50:38 -0700 |
| commit | aa514ce34b65e3dc01f95a0b470b39bbb7e09998 (patch) | |
| tree | 6d83d3f8e7560e5cd46fafe39960cd78cdfdc815 /drivers/clk/clk-divider.c | |
| parent | 29f79cb713c5173457b80602adab357403f22c48 (diff) | |
clk: wrap I/O access for improved portability
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-divider.c')
| -rw-r--r-- | drivers/clk/clk-divider.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 749372f87ec..8d3009e44fb 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int div, val; - val = readl(divider->reg) >> divider->shift; + val = clk_readl(divider->reg) >> divider->shift; val &= div_mask(divider); div = _get_div(divider, val); @@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = div_mask(divider) << (divider->shift + 16); } else { - val = readl(divider->reg); + val = clk_readl(divider->reg); val &= ~(div_mask(divider) << divider->shift); } val |= value << divider->shift; - writel(val, divider->reg); + clk_writel(val, divider->reg); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); |