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author | Tomasz Figa <t.figa@samsung.com> | 2013-10-15 19:41:18 +0200 |
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committer | Tomasz Figa <t.figa@samsung.com> | 2013-12-30 18:15:48 +0100 |
commit | 3818f11740bbf87ad76f4f502f6739c8d62e5c17 (patch) | |
tree | 19cc5c3a76f11607db73d0bf500ea4da0f788de9 /drivers/clk/clk-si5351.c | |
parent | 796d1f4cd62500ee55a645f2649b546710b11bd1 (diff) |
clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/clk-si5351.c')
0 files changed, 0 insertions, 0 deletions