diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2013-01-04 12:30:57 +0530 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-01-24 11:12:58 -0800 |
| commit | 10290030d7d31e387f602190ece2cdb3abfb3d71 (patch) | |
| tree | 56d301a919571a34ef8ba456290331f2da1958f8 /drivers/clk/clk-zynq.c | |
| parent | 5b6e0adb69674c684c33503f50010644b049029c (diff) | |
clk: zynq: Use common of_clk_init() function
Use common of_clk_init() function for clock initialization.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-zynq.c')
| -rw-r--r-- | drivers/clk/clk-zynq.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c index 37a30514fd6..b14a25f3925 100644 --- a/drivers/clk/clk-zynq.c +++ b/drivers/clk/clk-zynq.c @@ -81,6 +81,7 @@ static void __init zynq_pll_clk_setup(struct device_node *np) if (WARN_ON(ret)) return; } +CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup); struct zynq_periph_clk { struct clk_hw hw; @@ -187,6 +188,7 @@ static void __init zynq_periph_clk_setup(struct device_node *np) if (WARN_ON(err)) return; } +CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup); /* CPU Clock domain is modelled as a mux with 4 children subclks, whose * derivative rates depend on CLK_621_TRUE @@ -366,18 +368,10 @@ static void __init zynq_cpu_clk_setup(struct device_node *np) if (WARN_ON(err)) return; } - -static const __initconst struct of_device_id zynq_clk_match[] = { - { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, - { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, }, - { .compatible = "xlnx,zynq-periph-clock", - .data = zynq_periph_clk_setup, }, - { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, }, - {} -}; +CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup); void __init xilinx_zynq_clocks_init(void __iomem *slcr) { slcr_base = slcr; - of_clk_init(zynq_clk_match); + of_clk_init(NULL); } |