Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...

1 files changed, 12 insertions, 6 deletions

diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index adaa4a1821b..25ceccf939a 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -45,8 +45,10 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 	clk_data.clk_num = 2 + desc->num_ratios;
 	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
 				GFP_KERNEL);
-	if (WARN_ON(!clk_data.clks))
+	if (WARN_ON(!clk_data.clks)) {
+		iounmap(base);
 		return;
+	}
 
 	/* Register TCLK */
 	of_property_read_string_index(np, "clock-output-names", 0,
@@ -134,7 +136,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
 
 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 	if (WARN_ON(!ctrl))
-		return;
+		goto ctrl_out;
 
 	spin_lock_init(&ctrl->lock);
 
@@ -145,10 +147,8 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
 	ctrl->num_gates = n;
 	ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
 			      GFP_KERNEL);
-	if (WARN_ON(!ctrl->gates)) {
-		kfree(ctrl);
-		return;
-	}
+	if (WARN_ON(!ctrl->gates))
+		goto gates_out;
 
 	for (n = 0; n < ctrl->num_gates; n++) {
 		const char *parent =
@@ -160,4 +160,10 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
 	}
 
 	of_clk_add_provider(np, clk_gating_get_src, ctrl);
+
+	return;
+gates_out:
+	kfree(ctrl);
+ctrl_out:
+	iounmap(base);
 }