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authorStephen Boyd <sboyd@codeaurora.org>2014-01-15 10:47:27 -0800
committerMike Turquette <mturquette@linaro.org>2014-01-16 12:01:02 -0800
commitb36ba30c8ac66249915c57be101180cc58c42085 (patch)
tree4dc542affa7a2a416e8f62f88f0adb16b6ba937f /drivers/clk/qcom/Makefile
parent6e0ad1b6c1c9809a8ea9ca647cbc0471e8b4164d (diff)
clk: qcom: Add reset controller support
Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/qcom/Makefile')
-rw-r--r--drivers/clk/qcom/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1b4f75f5803..ec12ec4568f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -5,3 +5,4 @@ clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
+clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o