diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-05-16 16:07:09 -0700 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-05-29 09:30:21 -0700 |
| commit | 437ae6a1b8f2eedebfbf0f6572e19ca5c58a3f71 (patch) | |
| tree | 920dbc7a6519b50374ea409702e05e209a3aa45b /drivers/clk/qcom | |
| parent | aa014149ba002155a084ec1e9328e95b70167cbb (diff) | |
clk: qcom: Fix mmcc-8974's PLL configurations
We forgot to add the status bit for the PLLs and we were using
the wrong register and masks for configuration, leading to
unexpected PLL configurations. Fix this.
Fixes: d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC))
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8974.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 60b7c24a5cd..62200bbc759 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -170,6 +170,7 @@ static struct clk_pll mmpll0 = { .config_reg = 0x0014, .mode_reg = 0x0000, .status_reg = 0x001c, + .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll0", .parent_names = (const char *[]){ "xo" }, @@ -193,9 +194,10 @@ static struct clk_pll mmpll1 = { .l_reg = 0x0044, .m_reg = 0x0048, .n_reg = 0x004c, - .config_reg = 0x0054, + .config_reg = 0x0050, .mode_reg = 0x0040, .status_reg = 0x005c, + .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll1", .parent_names = (const char *[]){ "xo" }, @@ -219,7 +221,7 @@ static struct clk_pll mmpll2 = { .l_reg = 0x4104, .m_reg = 0x4108, .n_reg = 0x410c, - .config_reg = 0x4114, + .config_reg = 0x4110, .mode_reg = 0x4100, .status_reg = 0x411c, .clkr.hw.init = &(struct clk_init_data){ @@ -234,9 +236,10 @@ static struct clk_pll mmpll3 = { .l_reg = 0x0084, .m_reg = 0x0088, .n_reg = 0x008c, - .config_reg = 0x0094, + .config_reg = 0x0090, .mode_reg = 0x0080, .status_reg = 0x009c, + .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3", .parent_names = (const char *[]){ "xo" }, @@ -2319,7 +2322,7 @@ static const struct pll_config mmpll1_config = { .vco_val = 0x0, .vco_mask = 0x3 << 20, .pre_div_val = 0x0, - .pre_div_mask = 0x3 << 12, + .pre_div_mask = 0x7 << 12, .post_div_val = 0x0, .post_div_mask = 0x3 << 8, .mn_ena_mask = BIT(24), @@ -2333,7 +2336,7 @@ static struct pll_config mmpll3_config = { .vco_val = 0x0, .vco_mask = 0x3 << 20, .pre_div_val = 0x0, - .pre_div_mask = 0x3 << 12, + .pre_div_mask = 0x7 << 12, .post_div_val = 0x0, .post_div_mask = 0x3 << 8, .mn_ena_mask = BIT(24), |