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authorPrashant Gaikwad <pgaikwad@nvidia.com>2013-01-11 13:16:24 +0530
committerStephen Warren <swarren@nvidia.com>2013-01-28 11:19:07 -0700
commit37c26a906527b8a6a252614ca83d21ad318c4e84 (patch)
tree8041c27e60eddd5030a83283162b1c39d50bdd98 /drivers/clk/tegra/Makefile
parent8f8f484bf355e546c62c47b8a8c8d19b28787798 (diff)
clk: tegra: add clock support for Tegra20
Add Tegra20 clock support based on common clock framework. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe, implemented KBC clock, ensure all OF lookups return valid cookies i.e. an explicit error pointer or valid pointer not NULL, adapt to renames in earlier patches, fixed some checkpatch issues.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/Makefile')
-rw-r--r--drivers/clk/tegra/Makefile2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 68bd353a210..00484fd4e51 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,3 +6,5 @@ obj-y += clk-periph-gate.o
obj-y += clk-pll.o
obj-y += clk-pll-out.o
obj-y += clk-super.o
+
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o