diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-18 16:11:38 +0100 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 18:46:53 +0200 |
| commit | b29f9e926442c35bd42ebd283aaed0de2c4f1477 (patch) | |
| tree | 478f053f15bf821bb82c7d8bc58ea1c861338082 /drivers/clk/tegra/clk.h | |
| parent | bc44275b8ea2df7c77658b08955ec545a37560ab (diff) | |
clk: tegra: add TEGRA_PERIPH_NO_GATE
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index f984ebed9f1..40fb011233c 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -391,6 +391,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_ON_APB BIT(2) #define TEGRA_PERIPH_WAR_1005168 BIT(3) #define TEGRA_PERIPH_NO_DIV BIT(4) +#define TEGRA_PERIPH_NO_GATE BIT(5) void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); extern const struct clk_ops tegra_clk_periph_gate_ops; |