diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-09-25 21:18:15 -0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-10-07 18:16:37 -0700 |
| commit | 6cfc229d6f967041b5e1ee56a5bb87a500f31311 (patch) | |
| tree | 79e0890000be71742fc06f587554d7f255619841 /drivers/clk | |
| parent | 7affe5685c962ed0bc0fadf307400484b2276c89 (diff) | |
clk: keystone: Build Keystone clock drivers
Now build the keystone common clock drivers. The build is made
conditional based on COMMON_CLK_KEYSTONE
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/clk/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/keystone/Makefile | 1 |
3 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index dd37f91289d..5c51115081b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -100,6 +100,13 @@ config COMMON_CLK_XGENE ---help--- Sypport for the APM X-Gene SoC reference, PLL, and device clocks. +config COMMON_CLK_KEYSTONE + tristate "Clock drivers for Keystone based SOCs" + depends on ARCH_KEYSTONE && OF + ---help--- + Supports clock drivers for Keystone based SOCs. These SOCs have local + a power sleep control module that gate the clock to the IPs and PLLs. + endmenu source "drivers/clk/mvebu/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 270f3fd2fbc..df33820b45e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ obj-$(CONFIG_X86) += x86/ diff --git a/drivers/clk/keystone/Makefile b/drivers/clk/keystone/Makefile new file mode 100644 index 00000000000..0477cf63f13 --- /dev/null +++ b/drivers/clk/keystone/Makefile @@ -0,0 +1 @@ +obj-y += pll.o gate.o |