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authorOlof Johansson <olof@lixom.net>2013-04-28 12:43:08 -0700
committerOlof Johansson <olof@lixom.net>2013-04-28 15:01:12 -0700
commitafcf7924ecab726dab0227188783c4a40d9f0eec (patch)
tree606b0883c0ad3fb2ef04f0f036a55ed3875fdc9b /drivers/clk
parentdc9c220304c882f06aaadf427821c6388782aab8 (diff)
parentd21be237ffa357e55005e2bf9ffef10b23c184d0 (diff)
Merge branch 'fixes' into next/cleanup
Merging in fixes since there's a conflict in the omap4 clock tables caused by it. * fixes: (245 commits) ARM: highbank: fix cache flush ordering for cpu hotplug ARM: OMAP4: hwmod data: make 'ocp2scp_usb_phy_phy_48m" as the main clock arm: mvebu: Fix the irq map function in SMP mode Fix GE0/GE1 init on ix2-200 as GE0 has no PHY ARM: S3C24XX: Fix interrupt pending register offset of the EINT controller ARM: S3C24XX: Correct NR_IRQS definition for s3c2440 ARM i.MX6: Fix ldb_di clock selection ARM: imx: provide twd clock lookup from device tree ARM: imx35 Bugfix admux clock ARM: clk-imx35: Bugfix iomux clock + Linux 3.9-rc6 Signed-off-by: Olof Johansson <olof@lixom.net> Conflicts: arch/arm/mach-omap2/cclock44xx_data.c
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b92d48be4cc..bf194009e20 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -703,7 +703,7 @@ static void tegra20_pll_init(void)
clks[pll_a_out0] = clk;
/* PLLE */
- clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
+ clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
0, 100000000, &pll_e_params,
0, pll_e_freq_table, NULL);
clk_register_clkdev(clk, "pll_e", NULL);