diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-07-19 10:16:45 -0700 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-08-20 07:54:41 +0200 |
| commit | 353dc6c47d67c83f7cc20334f8deb251674e6864 (patch) | |
| tree | 9a7659b80b911265cd06554929cdd89c02dd1f6e /drivers/clk | |
| parent | 14924ba288921c536a72e71baeb14322ece44b39 (diff) | |
clk/zynq/pll: Use #defines for fbdiv min/max values
Use more descriptive #defines for the minimum and maximum PLL
feedback divider.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/zynq/pll.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index 6daa7b6702e..3226f54fa59 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -50,6 +50,9 @@ struct zynq_pll { #define PLLCTRL_RESET_MASK 1 #define PLLCTRL_RESET_SHIFT 0 +#define PLL_FBDIV_MIN 13 +#define PLL_FBDIV_MAX 66 + /** * zynq_pll_round_rate() - Round a clock frequency * @hw: Handle between common and hardware-specific interfaces @@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, u32 fbdiv; fbdiv = DIV_ROUND_CLOSEST(rate, *prate); - if (fbdiv < 13) - fbdiv = 13; - else if (fbdiv > 66) - fbdiv = 66; + if (fbdiv < PLL_FBDIV_MIN) + fbdiv = PLL_FBDIV_MIN; + else if (fbdiv > PLL_FBDIV_MAX) + fbdiv = PLL_FBDIV_MAX; return *prate * fbdiv; } |