diff options
| author | Mikko Perttunen <mperttunen@nvidia.com> | 2014-07-11 17:18:29 +0300 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-09-18 13:57:12 +0300 |
| commit | 4c495c204f794125db11e74bd61228901b0acaa7 (patch) | |
| tree | abf4f4f7fe05c5748dc879749dd21b7f8ecc4393 /drivers/clk | |
| parent | d364a77d02071355edbd5ee26c248b1ea75c653c (diff) | |
clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks
These clocks are used as parents for some EMC timings.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 9525c684d14..e3a85842ce0 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1166,6 +1166,12 @@ static void __init tegra124_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_c_out1", NULL); clks[TEGRA124_CLK_PLL_C_OUT1] = clk; + /* PLLC_UD */ + clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", + CLK_SET_RATE_PARENT, 1, 1); + clk_register_clkdev(clk, "pll_c_ud", NULL); + clks[TEGRA124_CLK_PLL_C_UD] = clk; + /* PLLC2 */ clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, &pll_c2_params, NULL); @@ -1198,6 +1204,8 @@ static void __init tegra124_pll_init(void __iomem *clk_base, /* PLLM_UD */ clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", CLK_SET_RATE_PARENT, 1, 1); + clk_register_clkdev(clk, "pll_m_ud", NULL); + clks[TEGRA124_CLK_PLL_M_UD] = clk; /* PLLU */ val = readl(clk_base + pll_u_params.base_reg); |