diff options
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2014-04-30 14:39:37 +0300 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-06-06 20:33:34 +0300 |
| commit | 81c7e03acbcb68274be770134f8f04f270ffa859 (patch) | |
| tree | ca6115715324f00441d89cc4a08e6a6382b48687 /drivers/clk | |
| parent | 9ac33b0ce81fa48dd39e7ddfc1bf4519052181dd (diff) | |
CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ti/clk-54xx.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 08f3d1b915b..5e183993e3e 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -240,6 +240,12 @@ int __init omap5xxx_dt_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); + abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); + if (!rc) + rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); + if (rc) + pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); + usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); if (rc) |