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authorMichael Ellerman <michael@ellerman.id.au>2012-10-30 16:09:56 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-11-15 13:00:36 +1100
commitda111957796515755d95ec6773dc714350724a4e (patch)
tree4854509b69457adb40f1a82fb853920208c99238 /drivers/clocksource
parentbb29b719372742939af05457aff1b59608764e89 (diff)
powerpc/perf: Add missing L2 constraint handling in Power7 PMU
If we have two cache events that require different settings of the L2SEL bits in MMCR1 then we can not schedule those events simultaneously. Add logic to the constraint handling to express that. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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