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authorLi Peng <peng.li@linux.intel.com>2010-05-18 18:58:44 +0800
committerEric Anholt <eric@anholt.net>2010-05-26 14:22:51 -0700
commit9553426372eef71c849499fb1d232f4b0577c0f9 (patch)
tree8df1e5e08fd759c2c7279c232ef7e6732a3e65db /drivers/connector
parentd8201ab6514f8dc1a0ccfac52c688d80976a425a (diff)
drm/i915: Add CxSR support on Pineview DDR3
Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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