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authorDan Williams <dan.j.williams@intel.com>2009-09-08 17:42:57 -0700
committerDan Williams <dan.j.williams@intel.com>2009-09-08 17:42:57 -0700
commitb094ad3be564e7cc59cca4ff0256550d3a55dd3b (patch)
treed69f515b2ee6af2b0f12bb3028d7c7f5b3390794 /drivers/dma/ioat/registers.h
parente61dacaeb3918cd00cd642e8fb0828324ac59819 (diff)
ioat3: xor support
ioat3.2 adds xor offload support for up to 8 sources. It can also perform an xor-zero-sum operation to validate whether all given sources sum to zero, without writing to a destination. Xor descriptors differ from memcpy in that one operation may require multiple descriptors depending on the number of sources. When the number of sources exceeds 5 an extended descriptor is needed. These descriptors need to be accounted for when updating the DMA_COUNT register. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ioat/registers.h')
-rw-r--r--drivers/dma/ioat/registers.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
index 97d26ea6d72..63038e18ab0 100644
--- a/drivers/dma/ioat/registers.h
+++ b/drivers/dma/ioat/registers.h
@@ -243,6 +243,8 @@
#define IOAT_CHANERR_XOR_Q_ERR 0x20000
#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000
+#define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR)
+
#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
#endif /* _IOAT_REGISTERS_H_ */