diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-17 18:40:24 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-17 18:40:24 -0800 |
| commit | 57f2685c16fa8e0cb86e4bc7c8ac33bfed943819 (patch) | |
| tree | 96a42fe632687c8486c250c4805bf1d4c9c34d19 /drivers/dma/ste_dma40_ll.h | |
| parent | 488a9d018256dc9f29e041c0360445b6d25eea9a (diff) | |
| parent | e08b881a69d638175bfa99b5af4d72b731633ea7 (diff) | |
Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma
* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (53 commits)
ARM: mach-shmobile: specify CHCLR registers on SH7372
dma: shdma: fix runtime PM: clear channel buffers on reset
dma/imx-sdma: save irq flags when use spin_lock in sdma_tx_submit
dmaengine/ste_dma40: clear LNK on channel startup
dmaengine: intel_mid_dma: remove legacy pm interface
ASoC: mxs: correct 'direction' of device_prep_dma_cyclic
dmaengine: intel_mid_dma: error path fix
dmaengine: intel_mid_dma: locking and freeing fixes
mtd: gpmi-nand: move to dma_transfer_direction
mtd: fix compile error for gpmi-nand
mmc: mxs-mmc: fix the dma_transfer_direction migration
dmaengine: add DMA_TRANS_NONE to dma_transfer_direction
dma: mxs-dma: Don't use CLKGATE bits in CTRL0 to disable DMA channels
dma: mxs-dma: make mxs_dma_prep_slave_sg() multi user safe
dma: mxs-dma: Always leave mxs_dma_init() with the clock disabled.
dma: mxs-dma: fix a typo in comment
DMA: PL330: Remove pm_runtime_xxx calls from pl330 probe/remove
video i.MX IPU: Fix display connections
i.MX IPU DMA: Fix wrong burstsize settings
dmaengine/ste_dma40: allow fixed physical channel
...
Fix up conflicts in drivers/dma/{Kconfig,mxs-dma.c,pl330.c}
The conflicts looked pretty trivial, but I'll ask people to verify them.
Diffstat (limited to 'drivers/dma/ste_dma40_ll.h')
| -rw-r--r-- | drivers/dma/ste_dma40_ll.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index b44c455158d..8d3d490968a 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h @@ -16,6 +16,8 @@ #define D40_TYPE_TO_GROUP(type) (type / 16) #define D40_TYPE_TO_EVENT(type) (type % 16) +#define D40_GROUP_SIZE 8 +#define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2) /* Most bits of the CFG register are the same in log as in phy mode */ #define D40_SREG_CFG_MST_POS 15 @@ -123,6 +125,15 @@ /* DMA Register Offsets */ #define D40_DREG_GCC 0x000 +#define D40_DREG_GCC_ENA 0x1 +/* This assumes that there are only 4 event groups */ +#define D40_DREG_GCC_ENABLE_ALL 0xff01 +#define D40_DREG_GCC_EVTGRP_POS 8 +#define D40_DREG_GCC_SRC 0 +#define D40_DREG_GCC_DST 1 +#define D40_DREG_GCC_EVTGRP_ENA(x, y) \ + (1 << (D40_DREG_GCC_EVTGRP_POS + 2 * x + y)) + #define D40_DREG_PRTYP 0x004 #define D40_DREG_PRSME 0x008 #define D40_DREG_PRSMO 0x00C |