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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2014-05-08 12:01:48 +0300
committerVinod Koul <vinod.koul@intel.com>2014-05-22 15:37:24 +0530
commitd2f78e95e42a9130002c76f1a1f76e657a4b4004 (patch)
treeba270d4a8ca0666bd753f3bad9088a113730452a /drivers/dma
parentfbeb91fe8e4107dc88df4eaa21de02c3fd9d1cd5 (diff)
dmaengine: dw: enable clock before access
hclk signal is a bus clock. So, it means we have to have it enabled during access to the DMA controller. This patch makes sure that we enable clock before access to the device, though it currently works on Intel hardware. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/dw/core.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 7a740769c2f..009dc62f943 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1493,6 +1493,11 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
dw->regs = chip->regs;
chip->dw = dw;
+ dw->clk = devm_clk_get(chip->dev, "hclk");
+ if (IS_ERR(dw->clk))
+ return PTR_ERR(dw->clk);
+ clk_prepare_enable(dw->clk);
+
dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
autocfg = dw_params >> DW_PARAMS_EN & 0x1;
@@ -1520,11 +1525,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
if (!dw->chan)
return -ENOMEM;
- dw->clk = devm_clk_get(chip->dev, "hclk");
- if (IS_ERR(dw->clk))
- return PTR_ERR(dw->clk);
- clk_prepare_enable(dw->clk);
-
/* Get hardware configuration parameters */
if (autocfg) {
max_blk_size = dma_readl(dw, MAX_BLK_SIZE);