diff options
| author | Borislav Petkov <borislav.petkov@amd.com> | 2009-12-15 16:03:53 +0100 |
|---|---|---|
| committer | Borislav Petkov <borislav.petkov@amd.com> | 2009-12-16 17:48:39 +0100 |
| commit | 256f7276af20c88b492353710d5d6640b09c3d63 (patch) | |
| tree | 9d2a4a26da9d79b3d19dafa9cf44149a1cee7a28 /drivers/edac/edac_mce_amd.c | |
| parent | 35d8069234bacfab608d2d7571c2cb71a23c3fae (diff) | |
edac, mce, amd: silence GART TLB errors
Although reporting of benign GART TLB errors is disabled in
__mcheck_cpu_apply_quirks, those are still being logged, and, as a
result, trip up amd64_edac. Pull up reporting check so that machines
with loaded edac module bail out early and don't spit fragments into
dmesg.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/edac_mce_amd.c')
| -rw-r--r-- | drivers/edac/edac_mce_amd.c | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c index 9965b8daca7..8fc91a01962 100644 --- a/drivers/edac/edac_mce_amd.c +++ b/drivers/edac/edac_mce_amd.c @@ -299,6 +299,12 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) if (!handle_errors) return; + /* + * GART TLB error reporting is disabled by default. Bail out early. + */ + if (TLB_ERROR(ec) && !report_gart_errors) + return; + pr_emerg(" Northbridge Error, node %d", node_id); /* @@ -332,21 +338,6 @@ static void amd_decode_fr_mce(u64 mc5_status) static inline void amd_decode_err_code(unsigned int ec) { if (TLB_ERROR(ec)) { - /* - * GART errors are intended to help graphics driver developers - * to detect bad GART PTEs. It is recommended by AMD to disable - * GART table walk error reporting by default[1] (currently - * being disabled in mce_cpu_quirks()) and according to the - * comment in mce_cpu_quirks(), such GART errors can be - * incorrectly triggered. We may see these errors anyway and - * unless requested by the user, they won't be reported. - * - * [1] section 13.10.1 on BIOS and Kernel Developers Guide for - * AMD NPT family 0Fh processors - */ - if (!report_gart_errors) - return; - pr_emerg(" Transaction: %s, Cache Level %s\n", TT_MSG(ec), LL_MSG(ec)); } else if (MEM_ERROR(ec)) { |