diff options
| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-27 09:16:06 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-30 14:56:52 -0300 |
| commit | 15154c57c62494292f43df9133a7b370cbbf1ecb (patch) | |
| tree | f09c89b63f11ea4d28d867ce6990e702879dbb27 /drivers/edac | |
| parent | bb81a21637f84e2192bf327575645a7843c70cdb (diff) | |
i7300_edac: Properly detect the type of error correction
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/i7300_edac.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c index a88742abf1f..b5152256967 100644 --- a/drivers/edac/i7300_edac.c +++ b/drivers/edac/i7300_edac.c @@ -450,14 +450,24 @@ static int decode_mtr(struct i7300_pvt *pvt, p_csrow->mtype = MEM_FB_DDR2; /* - * FIXME: the type of error detection actually depends of the + * The type of error detection actually depends of the * mode of operation. When it is just one single memory chip, at - * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. - * In normal or mirrored mode, it uses Single Device Data correction, + * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. + * In normal or mirrored mode, it uses Lockstep mode, * with the possibility of using an extended algorithm for x8 memories * See datasheet Sections 7.3.6 to 7.3.8 */ - p_csrow->edac_mode = EDAC_S8ECD8ED; + + if (IS_SINGLE_MODE(pvt->mc_settings_a)) { + p_csrow->edac_mode = EDAC_SECDED; + debugf0("ECC code is 8-byte-over-32-byte SECDED+ code\n"); + } else { + debugf0("ECC code is on Lockstep mode\n"); + if (MTR_DRAM_WIDTH(mtr)) + p_csrow->edac_mode = EDAC_S8ECD8ED; + else + p_csrow->edac_mode = EDAC_S4ECD4ED; + } /* ask what device type on this row */ if (MTR_DRAM_WIDTH(mtr)) { |