diff options
| author | Li Peng <peng.li@linux.intel.com> | 2010-05-18 18:58:44 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-05-26 14:22:51 -0700 |
| commit | 9553426372eef71c849499fb1d232f4b0577c0f9 (patch) | |
| tree | 8df1e5e08fd759c2c7279c232ef7e6732a3e65db /drivers/gpu/drm/i915/i915_dma.c | |
| parent | d8201ab6514f8dc1a0ccfac52c688d80976a425a (diff) | |
drm/i915: Add CxSR support on Pineview DDR3
Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.
Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_dma.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 12e92f2cc3a..a5f40166484 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1491,6 +1491,10 @@ static void i915_pineview_get_mem_freq(struct drm_device *dev) dev_priv->mem_freq = 800; break; } + + /* detect pineview DDR3 setting */ + tmp = I915_READ(CSHRDDR3CTL); + dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; } static void i915_ironlake_get_mem_freq(struct drm_device *dev) |