diff options
| author | Li Peng <peng.li@linux.intel.com> | 2010-05-18 18:58:44 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-05-26 14:22:51 -0700 |
| commit | 9553426372eef71c849499fb1d232f4b0577c0f9 (patch) | |
| tree | 8df1e5e08fd759c2c7279c232ef7e6732a3e65db /drivers/gpu/drm/i915/i915_drv.h | |
| parent | d8201ab6514f8dc1a0ccfac52c688d80976a425a (diff) | |
drm/i915: Add CxSR support on Pineview DDR3
Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.
Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cccf8019f65..e6b4cab6565 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -326,7 +326,7 @@ typedef struct drm_i915_private { int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ int num_fence_regs; /* 8 on pre-965, 16 otherwise */ - unsigned int fsb_freq, mem_freq; + unsigned int fsb_freq, mem_freq, is_ddr3; spinlock_t error_lock; struct drm_i915_error_state *first_error; |