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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2014-10-29 11:32:32 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-07 18:41:43 +0100
commit3e369b76ceb625dffabef6f1c52e32fc0998843e (patch)
tree57a2a973fd4b5f86c7addb25ffe257ead5c94b77 /drivers/gpu/drm/i915/i915_drv.h
parent1e6f2ddc88fec990ef4fb1aa3b7cb9941df0321b (diff)
drm/i915: Move dpll crtc_mask and hw_state fields into separate struct
The new struct will be used in a follow up patch to allow a current and a staged config to exist for the same shared DPLL. v2: Rebase on by mask_to_refcount()->hweight32() change. (Damien) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f4eef701ce..62a8e058d7d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -229,14 +229,18 @@ struct intel_dpll_hw_state {
uint32_t wrpll;
};
-struct intel_shared_dpll {
+struct intel_shared_dpll_config {
unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
+ struct intel_dpll_hw_state hw_state;
+};
+
+struct intel_shared_dpll {
+ struct intel_shared_dpll_config config;
int active; /* count of number of active CRTCs (i.e. DPMS on) */
bool on; /* is the PLL actually active? Disabled during modeset */
const char *name;
/* should match the index in the dev_priv->shared_dplls array */
enum intel_dpll_id id;
- struct intel_dpll_hw_state hw_state;
/* The mode_set hook is optional and should be used together with the
* intel_prepare_shared_dpll function. */
void (*mode_set)(struct drm_i915_private *dev_priv,