diff options
| author | Satheeshakrishna M <satheeshakrishna.m@intel.com> | 2014-11-13 14:55:14 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-11-14 11:17:58 +0100 |
| commit | 429d47d524b0c986d5354814077ac5beede5fb68 (patch) | |
| tree | c2d4d32322b0c8c3ea3e495911be849717b0293f /drivers/gpu/drm/i915/i915_drv.h | |
| parent | 326ac39b68e6aeb57d81c60c6078989955c225b5 (diff) | |
drm/i915/skl: Structure/enum definitions for SKL clocks
Adding structure/enum for SKL clocking implementation.
v2: Addressed Damien's comment
- Removed internal structure from this header file
v3: Stove this into the generic intel_dpll_id enum and give them the established
DPLL_ID_ prefixes. (Daniel)
v4: - We'll only try to share DPLL1/2/3, leaving DPLL0 to eDP
- Use SKL in the skylake shared DPLL names
- Re-add the skl_dpll enum
(Damien)
v5: Remove SKL_DPLL_NONE (Daniel)
v6: Modified as per review comments from Paulo
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v4,v5)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3f3035ce30e..08128fbe918 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -213,10 +213,15 @@ enum intel_dpll_id { /* real shared dpll ids must be >= 0 */ DPLL_ID_PCH_PLL_A = 0, DPLL_ID_PCH_PLL_B = 1, + /* hsw/bdw */ DPLL_ID_WRPLL1 = 0, DPLL_ID_WRPLL2 = 1, + /* skl */ + DPLL_ID_SKL_DPLL1 = 0, + DPLL_ID_SKL_DPLL2 = 1, + DPLL_ID_SKL_DPLL3 = 2, }; -#define I915_NUM_PLLS 2 +#define I915_NUM_PLLS 3 struct intel_dpll_hw_state { /* i9xx, pch plls */ @@ -256,6 +261,11 @@ struct intel_shared_dpll { struct intel_dpll_hw_state *hw_state); }; +#define SKL_DPLL0 0 +#define SKL_DPLL1 1 +#define SKL_DPLL2 2 +#define SKL_DPLL3 3 + /* Used by dp and fdi links */ struct intel_link_m_n { uint32_t tu; |