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authorImre Deak <imre.deak@intel.com>2014-11-10 15:34:33 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-14 10:29:17 +0100
commit132f3f1767dbabfb01f3c9bd63098c65d91eeac9 (patch)
tree186332698ba674b92ad1e0b38c896eba7182588c /drivers/gpu/drm/i915/i915_irq.c
parentb900b949674464d6ede123fb352d3a63690e31ab (diff)
drm/i915: WARN if we receive any gen9 rps interrupts
Paulo noticed that we don't support RPS on GEN9 yet, so WARN for and ignore any RPS interrupts on that platform. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 96d150f575d..729e9a329f7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1690,6 +1690,11 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
* the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
{
+ /* TODO: RPS on GEN9 is not supported yet. */
+ if (WARN_ONCE(INTEL_INFO(dev_priv)->gen == 9,
+ "GEN9: unexpected RPS IRQ\n"))
+ return;
+
if (pm_iir & dev_priv->pm_rps_events) {
spin_lock(&dev_priv->irq_lock);
dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;