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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2013-07-12 16:35:14 -0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-07-19 18:08:09 +0200
commit23a78516081c49398b6bf08d7a40e954048426bf (patch)
tree26bab7c6907548a19499ca339b6c19f7c561ad37 /drivers/gpu/drm/i915/i915_irq.c
parent27b9188e14f5f1033ed36ea84035898fe21e4f46 (diff)
drm/i915: POSTING_READ(DEIER) on ivybridge_irq_handler
We have this POSTING_READ inside ironlake_irq_handler. I suppose we also want it on IVB because we want to stop the IRQ handler as soon as possible at this point. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3ef8f23d4fa..597a3d5ae7e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1305,6 +1305,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
/* disable master interrupt before clearing iir */
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+ POSTING_READ(DEIER);
/* Disable south interrupts. We'll only write to SDEIIR once, so further
* interrupts will will be stored on its back queue, and then we'll be