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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-11 09:49:58 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-11 09:49:58 +0100
commit8b3016c4f4cded41d4d53da6f09f40efd6083f4f (patch)
tree9667a158b5309d1cc01094a6d5b7c40f3ea00636 /drivers/gpu/drm/i915/i915_reg.h
parent021357acc8ea85273a9882b3fe89935629f51b12 (diff)
parentdd8849c8f59ec1cee4809a0c5e603e045abe860e (diff)
Merge branch 'drm-intel-fixes' into drm-intel-next
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbf58e0f258..db22a23c65a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2215,9 +2215,17 @@
#define WM1_LP_SR_EN (1<<31)
#define WM1_LP_LATENCY_SHIFT 24
#define WM1_LP_LATENCY_MASK (0x7f<<24)
+#define WM1_LP_FBC_LP1_MASK (0xf<<20)
+#define WM1_LP_FBC_LP1_SHIFT 20
#define WM1_LP_SR_MASK (0x1ff<<8)
#define WM1_LP_SR_SHIFT 8
#define WM1_LP_CURSOR_MASK (0x3f)
+#define WM2_LP_ILK 0x4510c
+#define WM2_LP_EN (1<<31)
+#define WM3_LP_ILK 0x45110
+#define WM3_LP_EN (1<<31)
+#define WM1S_LP_ILK 0x45120
+#define WM1S_LP_EN (1<<31)
/* Memory latency timer register */
#define MLTR_ILK 0x11222