diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-04-04 15:13:42 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-04-18 09:43:19 +0200 |
| commit | a6f429a5a2f6ae0e1e8df2493884f9a881486d81 (patch) | |
| tree | 467d802032ad600e98201ff1756cfc15e9d446da /drivers/gpu/drm/i915/i915_reg.h | |
| parent | a65c2fcd00518b7339d72e08e6b2b4261fbcc22a (diff) | |
drm/i915: Configure GAM_ECOCHK appropriatly for Gen7
IVB and HSW use different encodings for the PPGTT cacheability bits in
the GAM_ECOCHK register.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 96b361f9a32..3b9ec9bcd38 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -125,6 +125,11 @@ #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) #define ECOCHK_PPGTT_CACHE64B (0x3<<3) #define ECOCHK_PPGTT_CACHE4B (0x0<<3) +#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) +#define ECOCHK_PPGTT_LLC_IVB (0x1<<3) +#define ECOCHK_PPGTT_UC_HSW (0x1<<3) +#define ECOCHK_PPGTT_WT_HSW (0x2<<3) +#define ECOCHK_PPGTT_WB_HSW (0x3<<3) #define GAC_ECO_BITS 0x14090 #define ECOBITS_SNB_BIT (1<<13) |