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authorBen Widawsky <ben@bwidawsk.net>2013-04-05 13:12:43 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-08 20:53:05 +0200
commit88a2b2a32d71aad6d8dcd843294b00a204faa66b (patch)
treeec91711acdc5dd1e233293bdd7f86af615ed4fa5 /drivers/gpu/drm/i915/i915_reg.h
parentab5c608b2d96c8db80b9c7df072f18f3a4226b55 (diff)
drm/i915: Don't wait for PCH on reset
BIOS should be setting this, but in case it doesn't... v2: Define the bits we actually want to clear (Jesse) Make it an RMW op (Jesse) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058686c0dbb..0e4b7fb7d69 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3568,6 +3568,9 @@
#define DISP_ARB_CTL 0x45000
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
#define DISP_FBC_WM_DIS (1<<15)
+#define GEN7_MSG_CTL 0x45010
+#define WAIT_FOR_PCH_RESET_ACK (1<<1)
+#define WAIT_FOR_PCH_FLR_ACK (1<<0)
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 0x7010