diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-05 12:05:57 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-10 16:06:30 +0200 |
| commit | ee2b0b382a7e6cbf3549559ec7dc86c63f5aa3d1 (patch) | |
| tree | 1622293948061a4510ac3cb285b4fdf2a6a09440 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 5dc5298bb3e5d72af6bab5c1d43dad9a07052982 (diff) | |
drm/i915: add haswell_set_pipeconf
It's a copy of ironlake_set_pipeconf with 2 differences:
- There is no BPC field to set.
- The interlaced mask is now 2 bits instead of 3.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d1b58d047e7..fd9a319b86a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2639,6 +2639,7 @@ #define PIPECONF_GAMMA (1<<24) #define PIPECONF_FORCE_BORDER (1<<25) #define PIPECONF_INTERLACE_MASK (7 << 21) +#define PIPECONF_INTERLACE_MASK_HSW (3 << 21) /* Note that pre-gen3 does not support interlaced display directly. Panel * fitting must be disabled on pre-ilk for interlaced. */ #define PIPECONF_PROGRESSIVE (0 << 21) |