diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-04-14 14:17:47 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-04-16 11:13:11 -0700 |
| commit | f544847fbaf099278343f875987a983f2b913134 (patch) | |
| tree | 3d0fa173125c6e5725c441d1af27fb38baa07241 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | cd97824994042b809493807ea644ba26c0c23290 (diff) | |
drm/i915: allow tiled front buffers on 965+
This patch corrects a pretty big oversight in the KMS code for 965+
chips. The current code is missing tiled surface register programming,
so userland can allocate a tiled surface and use it for mode setting,
resulting in corruption. This patch fixes that, allowing for tiled
front buffers on 965+.
Cc: stable@kernel.org
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e805b590ae7..52119473226 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1446,6 +1446,7 @@ #define DISPPLANE_NO_LINE_DOUBLE 0 #define DISPPLANE_STEREO_POLARITY_FIRST 0 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TILED (1<<10) #define DSPAADDR 0x70184 #define DSPASTRIDE 0x70188 #define DSPAPOS 0x7018C /* reserved */ |