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authorLinus Torvalds <torvalds@linux-foundation.org>2009-05-29 08:48:13 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-05-29 08:48:13 -0700
commit3da9e9d34ed7d2f5c33fd194d9dd09e15f4e51c0 (patch)
tree676f0a5cbdec0e21ac3a69f077037303a612633a /drivers/gpu/drm/i915/i915_reg.h
parent44ada1a147fa28ae15b83a031c48fc2b992cc3ef (diff)
parent07f4f3e8a24138ca2f3650723d670df25687cd05 (diff)
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: i915: Set object to gtt domain when faulting it back in drm/i915: Apply a big hammer to 865 GEM object CPU cache flushing. drm/i915: Fix tiling pitch handling on 8xx.
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9668cc0d7f4..375569d01d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -190,7 +190,8 @@
#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
#define I830_FENCE_PITCH_SHIFT 4
#define I830_FENCE_REG_VALID (1<<0)
-#define I830_FENCE_MAX_PITCH_VAL 0x10
+#define I915_FENCE_MAX_PITCH_VAL 0x10
+#define I830_FENCE_MAX_PITCH_VAL 6
#define I830_FENCE_MAX_SIZE_VAL (1<<8)
#define I915_FENCE_START_MASK 0x0ff00000