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author | Takashi Iwai <tiwai@suse.de> | 2014-08-04 18:28:21 +0200 |
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committer | Takashi Iwai <tiwai@suse.de> | 2014-08-04 18:28:21 +0200 |
commit | e9e3bdffe38b256f920eacc455d30deba5e97655 (patch) | |
tree | cfa546f6370c117e012c12605da22ce189542127 /drivers/gpu/drm/i915/i915_reg.h | |
parent | f42bb22243d2ae264d721b055f836059fe35321f (diff) | |
parent | ae34a78c430c37c06404f032fb04e51315204281 (diff) |
Merge tag 'asoc-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for v3.17
This has been a pretty exciting release in terms of the framework, we've
finally got support for multiple CODECs attached to a single DAI link
which has been something there's been interest in as long as I've been
working on ASoC. A big thanks to Benoit and Misael for their work on
this.
Otherwise it's been a fairly standard release for development, including
more componentisation work from Lars-Peter and a good selection of both
CODEC and CPU drivers.
- Support for multiple CODECs attached to a single DAI, enabling
systems with for example multiple DAC/speaker drivers on a single
link, contributed by Benoit Cousson based on work from Misael Lopez
Cruz.
- Support for byte controls larger than 256 bytes based on the use of
TLVs contributed by Omair Mohammed Abdullah.
- More componentisation work from Lars-Peter Clausen.
- The remainder of the conversions of CODEC drivers to params_width()
- Drivers for Cirrus Logic CS4265, Freescale i.MX ASRC blocks, Realtek
RT286 and RT5670, Rockchip RK3xxx I2S controllers and Texas Instruments
TAS2552.
- Lots of updates and fixes, especially to the DaVinci, Intel,
Freescale, Realtek, and rcar drivers.
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e691b30b281..a5bab61bfc0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -942,6 +942,9 @@ enum punit_power_well { /* * Instruction and interrupt control regs */ +#define PGTBL_CTL 0x02020 +#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ +#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ #define PGTBL_ER 0x02024 #define RENDER_RING_BASE 0x02000 #define BSD_RING_BASE 0x04000 |