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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-12-17 14:19:02 -0800
committerChris Wilson <chris@chris-wilson.co.uk>2010-12-18 11:07:02 +0000
commit3b8d8d91d51c7d15cda51052624169edf7b6dbc6 (patch)
treef4b4f830d3d882f0d1673e21c15932843005a745 /drivers/gpu/drm/i915/i915_suspend.c
parent9c3d2f7ffac34c62fea0b73e607707168a6f09b1 (diff)
drm/i915: dynamic render p-state support for Sandy Bridge
Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a311809f3c8..f623efdb115 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -817,8 +817,10 @@ int i915_save_state(struct drm_device *dev)
dev_priv->saveIMR = I915_READ(IMR);
}
- if (HAS_PCH_SPLIT(dev))
+ if (IS_IRONLAKE_M(dev))
ironlake_disable_drps(dev);
+ if (IS_GEN6(dev))
+ gen6_disable_rps(dev);
intel_disable_clock_gating(dev);
@@ -867,11 +869,14 @@ int i915_restore_state(struct drm_device *dev)
/* Clock gating state */
intel_enable_clock_gating(dev);
- if (HAS_PCH_SPLIT(dev)) {
+ if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
intel_init_emon(dev);
}
+ if (IS_GEN6(dev))
+ gen6_enable_rps(dev_priv);
+
/* Cache mode state */
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);