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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-07 11:01:36 +0100 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-08-09 11:24:35 -0700 |
| commit | 5ddb954b9ee50824977d2931e0ff58b3050b337d (patch) | |
| tree | 11812f1a8d79c2a6dedf9091250810f600e74683 /drivers/gpu/drm/i915/intel_display.c | |
| parent | 913d8d110078788c14812dce8bb62c37946821d2 (diff) | |
drm/i915/edp: Flush the write before waiting for PLLs
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0bf683dd512..2a32a7b60c9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1665,6 +1665,7 @@ static void ironlake_enable_pll_edp (struct drm_crtc *crtc) dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); + POSTING_READ(DP_A); udelay(200); } |