diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-01-12 05:38:31 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-01-15 14:13:06 -0800 |
| commit | 885a5fb5b120a5c7e0b3baad7b0feb5a89f76c18 (patch) | |
| tree | c0a636d952445b79d7e2301e1796b6c175c27c8a /drivers/gpu/drm/i915/intel_display.c | |
| parent | 500a8cc466a24e2fbc4c86ef9c6467ae2ffdeb0c (diff) | |
drm/i915: fix pixel color depth setting on eDP
Original DP mode_valid check didn't take pixel color depth into account,
which made one 1600x900 eDP panel's mode check invalid because of overclock,
but actually this 6bpc panel does can work with x1 lane at 2.7G. This one
trys to take bpp value properly both in mode validation and mode setting.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4b96a54b8e4..45da78ef4a9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2924,6 +2924,21 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, temp |= PIPE_8BPC; else temp |= PIPE_6BPC; + } else if (is_edp) { + switch (dev_priv->edp_bpp/3) { + case 8: + temp |= PIPE_8BPC; + break; + case 10: + temp |= PIPE_10BPC; + break; + case 6: + temp |= PIPE_6BPC; + break; + case 12: + temp |= PIPE_12BPC; + break; + } } else temp |= PIPE_8BPC; I915_WRITE(pipeconf_reg, temp); |