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authorDave Airlie <airlied@redhat.com>2014-11-12 10:29:34 +1000
committerDave Airlie <airlied@redhat.com>2014-11-12 17:53:30 +1000
commit51b44eb17b8ec6c83eac7772b4c8bc5887c5fbf7 (patch)
tree4125e1888cbc215ec4a365457505a407f48e5232 /drivers/gpu/drm/i915/intel_display.c
parentcc7096fb6d1dfbdac5e7e2675c046fd40646cc66 (diff)
parent206c5f60a3d902bc4b56dab2de3e88de5eb06108 (diff)
Merge tag 'v3.18-rc4' into drm-next
backmerge to get vmwgfx locking changes into next as the conflict with per-plane locking.
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1d2fa7f4523..31bb1d7acf9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4632,7 +4632,7 @@ static void vlv_update_cdclk(struct drm_device *dev)
* BSpec erroneously claims we should aim for 4MHz, but
* in fact 1MHz is the correct frequency.
*/
- I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
+ I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
}
/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -12831,6 +12831,9 @@ static struct intel_quirk intel_quirks[] = {
/* Acer C720 Chromebook (Core i3 4005U) */
{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
+ /* Apple Macbook 2,1 (Core 2 T7400) */
+ { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
+
/* Toshiba CB35 Chromebook (Celeron 2955U) */
{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },