diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-10 22:33:42 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-10 23:13:51 +0100 |
| commit | 8c4223bee91b771782f2ec07f2c85d81cdff3ed5 (patch) | |
| tree | 558dde85f520687cc0cfa4011847daacc4c216e4 /drivers/gpu/drm/i915/intel_display.c | |
| parent | d5e0d2f51977fe1f7fd6ee5c1a4476b43bad8f92 (diff) | |
drm/i915: Only call udelay() when waiting for clocks to stabilise
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 95c84164050..df410e4827e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1989,8 +1989,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if ((temp & DPLL_VCO_ENABLE) == 0) { I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); I915_READ(pch_dpll_reg); + udelay(200); } - udelay(200); if (HAS_PCH_CPT(dev)) { /* Be sure PCH DPLL SEL is set */ @@ -2136,8 +2136,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) } else DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); - udelay(100); - /* Disable PF */ I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); |