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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2013-04-17 18:15:49 -0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-05-10 21:56:53 +0200
commit0a790cdbfc526890af7dc41515a563f09e427129 (patch)
tree4313704bebd898aa4ca9b1e4d2bfbea4265773cb /drivers/gpu/drm/i915/intel_pm.c
parent7dd23ba0899bd1a203cc1d6e7878d7dfc910a511 (diff)
drm/i915: implement WADPOClockGatingDisable for LPT
This should prevent mode set failures on LPT. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Pimp the w/a tag to fit into Damien's new scheme.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 28cec57e3f8..1a765723d37 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4093,6 +4093,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D,
I915_READ(SOUTH_DSPCLK_GATE_D) |
PCH_LP_PARTITION_LEVEL_DISABLE);
+
+ /* WADPOClockGatingDisable:hsw */
+ I915_WRITE(_TRANSA_CHICKEN1,
+ I915_READ(_TRANSA_CHICKEN1) |
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
static void lpt_suspend_hw(struct drm_device *dev)