diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-08 21:07:28 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-08 21:20:27 +0100 |
| commit | 1af5fa1b7e5ff8332f8a2ee3c5fb44d93b34868d (patch) | |
| tree | 7839004c008fe526a8fe94edae350d137d3d640b /drivers/gpu/drm/i915 | |
| parent | 2c9d97545914cc764786702f361a1f1c9bb8dfa9 (diff) | |
drm/i915/dp: Flush the PLL register write before sleeping
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 27805a9ca87..c7aa29bfdea 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -883,6 +883,7 @@ static void ironlake_edp_pll_off(struct drm_encoder *encoder) dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); + POSTING_READ(DP_A); udelay(200); } |