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authorBen Skeggs <bskeggs@redhat.com>2014-09-08 13:38:02 +1000
committerBen Skeggs <bskeggs@redhat.com>2014-09-15 22:25:09 +1000
commit64804a6d513cba428ed0e9b5cac8967e4c24a180 (patch)
tree9cca5bf386ffb4471fa275f65609b6ed97a7f20d /drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
parentd9b5f261db53db32d528698fa2330f6cda1a6292 (diff)
drm/gk104-/fb/ram: use parsed timing data in mr routines
All the other chipsets should be moved over to this too. It's not needed yet for the upcoming commits, so left this step as it'll conflict badly with Roy's GT21x reclocking work. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c')
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
index f84c6542c3c..3d77fc5add7 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
@@ -72,8 +72,13 @@ nouveau_sddr3_calc(struct nouveau_ram *ram)
{
struct nouveau_bios *bios = nouveau_bios(ram);
int CWL, CL, WR, DLL = 0, ODT = 0;
+ u8 ver;
- switch (!!ram->timing.data * ram->timing.version) {
+ ver = !!ram->timing.data * ram->timing.version;
+ if (ram->next)
+ ver = ram->next->bios.timing_ver;
+
+ switch (ver) {
case 0x10:
if (ram->timing.size < 0x17) {
/* XXX: NV50: Get CWL from the timing register */
@@ -86,9 +91,9 @@ nouveau_sddr3_calc(struct nouveau_ram *ram)
ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x07;
break;
case 0x20:
- CWL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7;
- CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
- WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
+ CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
+ CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
+ WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
/* XXX: Get these values from the VBIOS instead */
DLL = !(ram->mr[1] & 0x1);
ODT = (ram->mr[1] & 0x004) >> 2 |