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authorBen Skeggs <bskeggs@redhat.com>2010-09-16 15:25:25 +1000
committerBen Skeggs <bskeggs@redhat.com>2010-09-24 16:26:49 +1000
commit855a95e4fc2ac6b758145ca7d6a0c95b66a57ef8 (patch)
treea8536a4799ee31a97186d44c6bdb5fa90f6e3919 /drivers/gpu/drm/nouveau/nouveau_bios.h
parentf9aafdd30ef8356f0a3690bf9bdd9c6e51b7705c (diff)
drm/nouveau: make the behaviour of get_pll_limits() consistent
This replaces all the pll_types definitions for ones that match the types used in the tables in recent VBIOS versions. get_pll_limits() will now accept either type or register value as input across all limits table versions, and will store the actual register ID that a PLL type refers to in the returned structure. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_bios.h')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h24
1 files changed, 18 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index c1de2f3fcb0..02c5dd09ba7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -170,16 +170,28 @@ enum LVDS_script {
LVDS_PANEL_OFF
};
-/* changing these requires matching changes to reg tables in nv_get_clock */
-#define MAX_PLL_TYPES 4
+/* these match types in pll limits table version 0x40,
+ * nouveau uses them on all chipsets internally where a
+ * specific pll needs to be referenced, but the exact
+ * register isn't known.
+ */
enum pll_types {
- NVPLL,
- MPLL,
- VPLL1,
- VPLL2
+ PLL_CORE = 0x01,
+ PLL_SHADER = 0x02,
+ PLL_UNK03 = 0x03,
+ PLL_MEMORY = 0x04,
+ PLL_UNK05 = 0x05,
+ PLL_UNK40 = 0x40,
+ PLL_UNK41 = 0x41,
+ PLL_UNK42 = 0x42,
+ PLL_VPLL0 = 0x80,
+ PLL_VPLL1 = 0x81,
+ PLL_MAX = 0xff
};
struct pll_lims {
+ u32 reg;
+
struct {
int minfreq;
int maxfreq;