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authorBen Skeggs <bskeggs@redhat.com>2011-12-13 11:57:55 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:05:46 +1000
commitc70c41e89f0481f26749d8264aebc594566c2a6d (patch)
tree9a112ff10ccbda529d70eecbedc5d763113846a0 /drivers/gpu/drm/nouveau/nouveau_mem.c
parent1072856a1c604726be6a8adfb6b2c86033e6a314 (diff)
drm/nv50: hopefully handle the DDR2/DDR3 memtype detection somewhat better
M version 2 appears to have a table with some form of memory type info available. NVIDIA appear to ignore the table information except for this DDR2/DDR3 case (which has the same value in 0x100714). My guess is this is due to some of the supported memory types not being represented in the table. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_mem.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 4a658310c29..c5ba6c2eab8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -683,6 +683,29 @@ nouveau_mem_timing_fini(struct drm_device *dev)
}
}
+int
+nouveau_mem_vbios_type(struct drm_device *dev)
+{
+ struct bit_entry M;
+ u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
+ if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
+ u8 *table = ROMPTR(dev, M.data[3]);
+ if (table && table[0] == 0x10 && ramcfg < table[3]) {
+ u8 *entry = table + table[1] + (ramcfg * table[2]);
+ switch (entry[0] & 0x0f) {
+ case 0: return NV_MEM_TYPE_DDR2;
+ case 1: return NV_MEM_TYPE_DDR3;
+ case 2: return NV_MEM_TYPE_GDDR3;
+ case 3: return NV_MEM_TYPE_GDDR5;
+ default:
+ break;
+ }
+
+ }
+ }
+ return NV_MEM_TYPE_UNKNOWN;
+}
+
static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{