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authorBen Skeggs <bskeggs@redhat.com>2011-12-11 00:30:05 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:05:20 +1000
commit7ad2d31cb692597f7918fce2f52a4c1949fbcf8d (patch)
tree7ff7f87196af92fb5de716da681d1b08961196bb /drivers/gpu/drm/nouveau/nv10_fb.c
parent83465324cb50e22b45ad53fd6e8887b1f8e43702 (diff)
drm/nouveau: move vram detection funcs to chipset-specific fb code
Also, display detected memory type in logs - though, we don't even try to detect this yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fb.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fb.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c
index f78181a59b4..7b17dea5f62 100644
--- a/drivers/gpu/drm/nouveau/nv10_fb.c
+++ b/drivers/gpu/drm/nouveau/nv10_fb.c
@@ -3,6 +3,41 @@
#include "nouveau_drv.h"
#include "nouveau_drm.h"
+int
+nv1a_fb_vram_init(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct pci_dev *bridge;
+ uint32_t mem, mib;
+
+ bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
+ if (!bridge) {
+ NV_ERROR(dev, "no bridge device\n");
+ return 0;
+ }
+
+ if (dev_priv->chipset == 0x1a) {
+ pci_read_config_dword(bridge, 0x7c, &mem);
+ mib = ((mem >> 6) & 31) + 1;
+ } else {
+ pci_read_config_dword(bridge, 0x84, &mem);
+ mib = ((mem >> 4) & 127) + 1;
+ }
+
+ dev_priv->vram_size = mib * 1024 * 1024;
+ return 0;
+}
+
+int
+nv10_fb_vram_init(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA);
+
+ dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
+ return 0;
+}
+
static struct drm_mm_node *
nv20_fb_alloc_tag(struct drm_device *dev, uint32_t size)
{