diff options
| author | Dave Airlie <airlied@redhat.com> | 2010-08-10 08:17:50 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-08-10 08:17:50 +1000 |
| commit | c3b6ef8633e75bdcde8e845548e3b95e9a21cdf6 (patch) | |
| tree | 4b97d4d8c955d0c62c2f0dc9dd1627ea07149a86 /drivers/gpu/drm/nouveau/nv50_crtc.c | |
| parent | d8ab35575098b2d6dc10b2535aeb40545933ae56 (diff) | |
| parent | 2dc5d2ec0599bd96729f8a9b00d44b56e15d765d (diff) | |
Merge remote branch 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next into drm-core-next
* 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next: (27 commits)
drm/nvc0: fix typo in PRAMIN flush
drm/nouveau: Fix DCB TMDS config parsing.
drm/nv30: Fix PFB init for nv31.
drm/nv04: Fix up SGRAM density detection.
drm/i2c/ch7006: Don't use POWER_LEVEL_FULL_POWER_OFF on early chip versions.
drm/nouveau: Init dcb->or on cards that have no usable DCB table.
drm/nouveau: reduce severity of some "error" messages
drm/nvc0: backup bar3 channel on suspend
drm/nouveau: implement init table opcodex 0x5e and 0x9a
drm/nouveau: implement init table op 0x57, INIT_LTIME
drm/nvc0: implement crtc pll setting
drm/nvc0: fix evo dma object so we display something
drm/nvc0: rudimentary instmem support
drm/nvc0: implement memory detection
drm/nvc0: allow INIT_GPIO
drm/nvc0: starting point for GF100 support, everything stubbed
drm/nv30: Workaround dual TMDS brain damage.
drm/nouveau: No need to set slave TV encoder configs explicitly.
drm/nv17-nv4x: Attempt to init some external TMDS transmitters.
drm/nv10: Fix up switching of NV10TCL_DMA_VTXBUF.
...
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_crtc.c | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index 5d11ea10166..a438e56a528 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c @@ -264,11 +264,16 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update) int nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) { - uint32_t reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head); + struct drm_nouveau_private *dev_priv = dev->dev_private; struct pll_lims pll; - uint32_t reg1, reg2; + uint32_t reg, reg1, reg2; int ret, N1, M1, N2, M2, P; + if (dev_priv->chipset < NV_C0) + reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head); + else + reg = 0x614140 + (head * 0x800); + ret = get_pll_limits(dev, reg, &pll); if (ret) return ret; @@ -286,7 +291,8 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) nv_wr32(dev, reg, 0x10000611); nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1); nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); - } else { + } else + if (dev_priv->chipset < NV_C0) { ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P); if (ret <= 0) return 0; @@ -298,6 +304,17 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) nv_wr32(dev, reg, 0x50000610); nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1); nv_wr32(dev, reg + 8, N2); + } else { + ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P); + if (ret <= 0) + return 0; + + NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", + pclk, ret, N1, N2, M1, P); + + nv_mask(dev, reg + 0x0c, 0x00000000, 0x00000100); + nv_wr32(dev, reg + 0x04, (P << 16) | (N1 << 8) | M1); + nv_wr32(dev, reg + 0x10, N2 << 16); } return 0; |