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| author | Ben Skeggs <bskeggs@redhat.com> | 2010-03-29 10:06:09 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2010-04-09 10:15:38 +1000 |
| commit | 6f335a7afa6bc57603f39430dc6f9e57de288a91 (patch) | |
| tree | 38b0a878a6272ebb22bf43ec296195e267b3a540 /drivers/gpu/drm/nouveau/nv50_display.c | |
| parent | d327dd4e771b5820743aeba0622116c5c8806388 (diff) | |
drm/nv50: preserve an unknown SOR_MODECTRL value for DP encoders
This value interacts with some registers we don't currently know how to
program properly ourselves. The default of 5 that we were using matches
what the VBIOS on early DP cards do, but later ones use 6, which would
cause nouveau to program an incorrect mode on these chips.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
0 files changed, 0 insertions, 0 deletions