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authorBen Skeggs <bskeggs@redhat.com>2010-11-22 16:05:54 +1000
committerFrancisco Jerez <currojerez@riseup.net>2010-12-08 03:00:34 +0100
commitd908175cca901b95ba1628428b216e6e7188e8fb (patch)
tree720e95c36101ca4fa2d46792c58bd2456c2df8db /drivers/gpu/drm/nouveau/nv50_fifo.c
parent395a31ec7ed9b02c5412f4405acbd6fceacca0fc (diff)
drm/nouveau: make fifo.create_context() responsible for mapping control regs
The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fifo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index ed18952ae7f..7add3dfde3d 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -261,6 +261,11 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
}
ramfc = chan->ramfc;
+ chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
+ NV50_USER(chan->id), PAGE_SIZE);
+ if (!chan->user)
+ return -ENOMEM;
+
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
@@ -327,6 +332,10 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the channel resources */
+ if (chan->user) {
+ iounmap(chan->user);
+ chan->user = NULL;
+ }
nouveau_gpuobj_ref(NULL, &ramfc);
nouveau_gpuobj_ref(NULL, &chan->cache);
}