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| author | Dave Airlie <airlied@redhat.com> | 2011-05-16 11:53:27 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-05-16 11:53:27 +1000 |
| commit | 46f2b6073430e14561f3aea1cee19b35223e0c04 (patch) | |
| tree | 30de66b80dcf23c3287384fa6b668ee4cd985d1a /drivers/gpu/drm/nouveau/nv50_pm.c | |
| parent | 69f7876b2ab61e8114675d6092ad0b482e233612 (diff) | |
| parent | b4fa9d0f6563756036f61c74fb38e3e97a1defd4 (diff) | |
Merge remote branch 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next into drm-core-next
* 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next: (55 commits)
drm/nouveau: make cursor_set implementation consistent with other drivers
drm/nva3/clk: better pll calculation when no fractional fb div available
drm/nouveau/pm: translate ramcfg strap through ram restrict table
drm/nva3/pm: allow use of divisor 16
drm/nvc0/pm: parse clock for pll 0x0a (0x137020) from perf table
drm/nvc0/pm: correct core/mem/shader perflvl parsing
drm/nouveau/pm: remove memtiming support check when assigning to perflvl
drm/nva3: support for memory timing map table
drm/nouveau: Associate memtimings with performance levels on cards <= nv98
drm/nva3/pm: initial pass at set_clock() hook
drm/nvc0/gr: calculate some more of our magic numbers
drm/nv50: respect LVDS link count from EDID on SPWG panels
drm/nouveau: recognise DCB connector type 0x41 as LVDS
drm/nouveau: fix uninitialised variable warning
drm/nouveau: Fix a crash at card takedown for NV40 and older cards
drm/nouveau: Free nv04 instmem ramin heap at card takedown
drm/nva3: somewhat improve clock reporting
drm/nouveau: pull refclk from vbios on limits 0x40 boards
drm/nv40/gr: oops, fix random bits getting set in engine obj
drm/nv50: improve nv50_pm_get_clock()
...
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_pm.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_pm.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c index 7dbb305d7e6..8a2810011bd 100644 --- a/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/drivers/gpu/drm/nouveau/nv50_pm.c @@ -47,6 +47,21 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id) reg0 = nv_rd32(dev, pll.reg + 0); reg1 = nv_rd32(dev, pll.reg + 4); + + if ((reg0 & 0x80000000) == 0) { + if (id == PLL_SHADER) { + NV_DEBUG(dev, "Shader PLL is disabled. " + "Shader clock is twice the core\n"); + ret = nv50_pm_clock_get(dev, PLL_CORE); + if (ret > 0) + return ret << 1; + } else if (id == PLL_MEMORY) { + NV_DEBUG(dev, "Memory PLL is disabled. " + "Memory clock is equal to the ref_clk\n"); + return pll.refclk; + } + } + P = (reg0 & 0x00070000) >> 16; N = (reg1 & 0x0000ff00) >> 8; M = (reg1 & 0x000000ff); |