Merge tag 'drm-intel-next-2012-06-21-merged' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next

Daniel writes:
 New -next pull request. Highlights:
 - Remaining vlv patches from Jesse et al.
 - Some hw workarounds from Jesse
 - hw context support from Ben
 - full uncore sharing on ivb
 - prep work to move the gtt code from intel-gtt.c to drm/i915 for gen6+
 - some backlight code improvements
 - leftovers for the timeout ioctl (we've forgotten the getparam)
 - ibx transcoder workarounds
 - some smaller fixlets and improvements
 - the new version of the "dont rely on HPD exclusively for VGA" patch

 Wrt regressions QA reported quite a few this time around.
 - The piglit/kernel-test fallout all has patches that are just awaiting
   review and merging into the next -next cycle.
 - Which just leaves a bunch of bugs about new modelines that don't work.
   It looks like these are all due to the new 16:9/16:10 modes in 3.5
   (yeah, only in this manual testing cycle did the git branch used by QA
   contain a backmerge of mainline with these patches).  Although I haven't
   yet confirmed this by letting our QA test the revert of that series.
 - Wrt bugs in general I'm trying to fight down some of our long-standing
   backlight issues (not regressions), but this seems to be a game of
   "you move, you lose" ... :("

Dropped merge bits since this had an -rc4 merge in it to fix some ugly
conflicts.

1 files changed, 9 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 01d77d1554f..3904d7964a4 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 	}
 
 	if (tiling_flags & RADEON_TILING_MACRO) {
-		if (rdev->family >= CHIP_CAYMAN)
+		if (rdev->family >= CHIP_TAHITI)
+			tmp = rdev->config.si.tile_config;
+		else if (rdev->family >= CHIP_CAYMAN)
 			tmp = rdev->config.cayman.tile_config;
 		else
 			tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 	} else if (tiling_flags & RADEON_TILING_MICRO)
 		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 
+	if ((rdev->family == CHIP_TAHITI) ||
+	    (rdev->family == CHIP_PITCAIRN))
+		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
+	else if (rdev->family == CHIP_VERDE)
+		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
+
 	switch (radeon_crtc->crtc_id) {
 	case 0:
 		WREG32(AVIVO_D1VGA_CONTROL, 0);